Testing integrated circuit (IC) functionality is critical throughout the entire lifetime of the product from development through high volume manufacturing. A device under test (DUT) board is an important element of the test hardware requirement to test ICs. As used herein, the term “integrated circuit” is meant to encompass both the IC device (i.e., semiconductor die) and its package (e.g., a packaged IC). The DUT board serves as the interconnection between a test socket for receiving the IC and automatic test equipment (ATE) for applying test vectors during testing the IC. Since the DUT board is at the center of the test system, designing and producing a DUT board requires knowledge of the IC to be tested and the ATE used in the test system, in particular, the number of tester channels of the ATE. A “tester channel” is a signal path between the DUT and the ATE.
One example of an IC is a programmable logic device (PLD), such as a field programmable gate array (FPGA) or a complex programmable logic device (CPLD). Present state of the art FPGAs, for example, include more than 1000 input/output (I/O) pins. Use of ATE that supplies a corresponding number of tester channels is costly and generally not economically feasible. To overcome this problem, DUT boards may be designed where several groups of I/O pins are shorted together such that there is one group of shorted I/O pins per tester channel of the ATE. Without the shorted pin approach, each I/O would require its own tester channel.
The developer of the test methodology for a given IC determines the best manner in which to short the I/O pins together. The developer must accurately communicate shorted-pin information for the IC to the manufacturer of the DUT board. Typically, the DUT manufacturer receives shorted-pin information via informal guidelines or non-documented word-of-mouth instructions. If incorrect information is passed to the DUT board manufacturer, the DUT board will not be constructed properly, leading to costly re-working of the DUT board or complete re-building of the DUT board. Such re-working or re-building of the DUT board further leads to delays in introducing new products to the market and extra expense. Moreover, some IC devices have many specialized I/Os, such as Joint Action Test Group (JTAG) I/Os. These specialized I/Os often exhibit limitations in that some special I/Os cannot be shorted with other special I/Os, which further complicates the information needed to manufacture a DUT board.
Accordingly, there exists a need in the art for systematically storing and providing shorted pin information for constructing a DUT board for a packaged integrated circuit.